Products

10G Backplane Applications (10GBASE-KR)

This family of CMOS devices, is targeted for transmission of 10G signals over backplane. The devices are designed to comply with the IEEE 802.3ap standard.

Benefits

Best-in-class integrated FEC/EDC/PHY/SerDes - ideal for use in dense backplane applications
High performance FEC function that allows for up to 40inches of FR4 trace length for large backplane applications
Low power-dissipating backplane SerDes device allows dense backplane architectures
Low-latency FEC implementation adds only 20ns to the single frame delay required by all decoders
Enhanced error statistics - useful for analyzing performance and tuning overall system settings
Enhanced BIST features simplify system-level link testing
Low latency of 120ns

Puma AEL3005	Single Channel 10G Backplane PHY/SerDes 10GBASE-KR (blade, ATCA, AMC, μTCA apps)
10GbE PHY/SerDes for line-cards and Mezzanine cards in blade systems, ATCA systems, AMC environments 10x10mm Package Integrated EDC and FEC functionality to meet IEEE802.3ap specifications Pre-emphasis and programmable rise/fall times on 10G transmitter Programmable bit and lane ordering Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source Multiple loop-back modes MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Supports up to 40 inches of backplane traces with 2 connectors Supports 1G transmission and auto-negotiation Proven interoperability (UNH) with other IEEE 802.3AP PHY/SerDes
Puma AEL3020	Dual Channel 10G Backplane PHY/SerDes 10GBASE-KR (blade, ATCA, AMC, μTCA apps)
10GbE PHY/SerDes for line-cards and Mezzanine cards in blade systems, ATCA systems, AMC environments 16x16mm Package Integrated EDC and FEC functionality to meet IEEE802.3ap specifications Pre-emphasis and programmable rise/fall times on 10G transmitter Programmable bit and lane ordering Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source Multiple loop-back modes MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Supports up to 40 inches of backplane traces with 2 connectors Supports 1G transmission and auto-negotiation Flexible power-down options to lower power consumption
Puma NLP3040	Quad Channel 10G Backplane PHY/SerDes 10GBASE-KR (blade, ATCA, AMC, μTCA apps)
10GbE PHY/SerDes for line-cards and Mezzanine cards in blade systems, ATCA systems, AMC environments 19x19mm Package Integrated EDC and FEC functionality to meet IEEE802.3ap specifications Pre-emphasis and programmable rise/fall times on 10G transmitter Programmable bit and lane ordering Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source Multiple loop-back modes MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Supports up to 40 inches of backplane traces with 2 connectors Supports 1G transmission and auto-negotiation Flexible power-down

Puma AEL3005
Puma AEL3020
Puma NLP3040

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