Products

10G PHY/SerDes for SFP+ Applications

This family of CMOS devices with XAUI and XFI back-ends, is designed for use with the emerging SFP+ module form-factor for the following applications:

With 10GBASE-SR/LR SFP+ modules (“Limiting”)
With 10GBASE-LRM SFP+ modules (“Linear”)
With 10GBASE-CR1 SFP+ direct-attached copper

Benefits

Best-in-class power consumption
Best-in-class package size
Optimized for line card/NIC applications with SFP+ modules
Highly integrated functionality resulting in smaller “effective footprint”
Fully qualified and shipping to end-customers
Complete product roadmap addressing customer requirements of multichannel PHY/SerDes, lower power consumption and higher levels of integration
Low latency of 120ns

Puma AEL1010	Single Channel SFI/XAUI PHY/SerDes (without EDC) SFP+ (Limiting Only)
10GbE PHY/SerDes (10G/XAUI) for line-cards and NICs with limiting SFP+ optical modules 13x13mm Package Enhanced 10G receiver with integrated limiting amplifier and equalization circuit Integrated WAN Interface Sub-layer (WIS) IEEE 802.3ae Clause 50-compliant Integrated clock synthesizer allows 156.25MHz to be synthesized from a 50 MHz input Multiple loop-back modes Full support for XENPAK, IEEE, and customer-specific register requirements MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Support for jumbo frames Programmable bit and lane ordering SONET-quality jitter performance
Puma AEL1020	Dual Channel SFI/XAUI PHY/SerDes (without EDC) SFP+ and QSFP+ (Limiting only)
10GbE PHY/SerDes (10G/XAUI) for line-cards and NICs with limiting SFP+/QSFP+ optical modules 16x16mm Package Enhanced 10G receiver with integrated limiting amplifier and equalization circuit TX pre-emphasis on the 10G and XAUI sides Integrated clock synthesizer allows 156.25MHz to be synthesized from a 50 MHz input Multiple loop-back modes Full support for XENPAK, IEEE, and customer-specific register requirements MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features SONET-quality jitter performance Programmable bit and lane ordering
Puma AEL2005	Single Channel SFI/XAUI PHY/SerDes (with EDC) SFP+ (Limiting, Linear and direct-attach Copper)
10GbE PHY/SerDes (10G/XAUI) for line-cards & NICs with SFP+ modules (limiting, linear and direct-attach copper) 15x15mm Package Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector Programmable bit & lane ordering Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source SONET-quality jitter performance Multiple loop-back modes MDIO, JTAG & SDA/SCL physical interfaces Built-in PRBS & BER Features Proven interoperability with SFP+ modules from several vendors Supports direct-attached copper (10GBASE-CR1) links exceeding 15 meters of twin-ax cable Supports up to 8 inches of FR4 traces to SFP+ module
Puma AEL2020	Dual Channel SFI/XAUI PHY/SerDes (with EDC) SFP+ and QSFP+ (Limiting, Linear and direct-attach Copper)
10GbE PHY/SerDes (10G/XAUI) for line-cards and NICs with SFP+ modules (limiting, linear and direct-attach copper) 16x16mm Package Integrated EDC functionality on 10G RX fully compliant with IEEE802.3aq specifications Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source SONET-quality jitter performance Multiple loop-back modes MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Proven interoperability with SFP+ modules from several vendors Supports direct-attached copper (10GBASE-CR1) links exceeding 15 meters of twin-ax cable Low power mode available Supports up to 8 inches of FR4 traces to SFP+ module
Puma AEL2003	Single Channel SFI/XFI Bridge (CDR with EDC) SFP+ (Limiting, Linear and direct-attach Copper)
10GbE PHY with integrated EDC for line-cards and NICs with SFP+ modules (limiting, linear and direct-attach copper) 10x10mm Package Integrated EDC functionality on 10G RX meets IEEE802.3aq specifications Integrated clock synthesizer allows 156.25MHz to be synthesized from a 50 MHz source SONET-quality jitter performance MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Proven interoperability with SFP+ modules from several vendors Supports direct-attached copper (10GBASE-CR1) links exceeding 15 meters of twin-ax cable Supports up to 8 inches of FR4 traces to SFP+ module
Puma AEL2006	Dual Channel SFI/XAUI Bridge (CDR with EDC) SFP+ and QSFP+ (Limiting, Linear and direct-attach Copper)
10GbE PHY with integrated EDC for line-cards and NICs with SFP+ modules (limiting,linear and direct-attach copper) 12x12mm Package Integrated EDC functionality on 10G RX meets IEEE802.3aq specifications Several loop-back modes MDIO, JTAG and SDA/SCL physical interfaces Pre-emphasis and programmable rise/fall times on SFI transmitter Adaptive equalizer on 10G XFI receiver Low power mode available SONET-quality jitter performance Built-in PRBS and BER Features Proven interoperability with SFP+ modules from several vendors Supports direct-attached copper (10GBASE-CR1) links exceeding 15 meters of twin-ax cable Supports up to 8 inches of FR4 traces to SFP+ module
Puma NLP2040	Quad Channel SFI/XAUI PHY/SerDes (with EDC) SFP+ and QSFP+ (Limiting, Linear and direct-attach Copper)
10GbE PHY/SerDes (10G/XAUI) for line-cards and NICs with SFP+ modules (limiting, linear and direct-attach copper) 19x19mm Package Integrated EDC functionality on 10G RX meets IEEE802.3aq specifications Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source SONET-quality jitter performance Multiple loop-back modes MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Proven interoperability with SFP+ modules from several vendors Supports direct-attached copper (10GBASE-CR1) links exceeding 15 meters of twin-ax cable Low power mode available Supports up to 8 inches of FR4 traces to SFP+ module
Puma NLP1042	Quad Channel SFI/XAUI PHY/SerDes (without EDC) SFP+ and QSFP+ (Limiting only)
10GbE PHY/SerDes (10G/XAUI) for line-cards and NICs with SFP+ modules (limiting only) 19x19mm Package One of the industry’s smallest quad-channel PHY/SerDes making it ideal for use in dense applications RXAUI (6.25G) system side interface eases PCB layout in high density switch applications Pre-emphasis and programmable rise/fall times on 10G transmitter Low latency makes it ideal for use in datacenter Ethernet applications Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source SONET-quality jitter performance Multiple loop-back modes MDIO, JTAG and SDA/SCL physical interfaces Built-in PRBS and BER Features Industry’s best-in-class per channel power consumption

Puma AEL1010
Puma AEL2005
Puma AEL2020
Puma AEL2003
Puma AEL2006
Puma AEL1020
Puma NLP1042
Puma NLP2040

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