PHY/SerDes IP

Multi-Standard, Multi-Rate (1-12.5Gbps) NLIP™ SerDes Macro

NetLogic Microsystems’ multi-standard, multi-rate SerDes macro consists of a quad-lane receiver and a quad-lane transmitter. The SerDes macro is optimized to support a wide range of data-rates from 1Gbps to 12.5Gbps. It can be incorporated in an integrated circuit to support a serial wireline interface.

Each of the four transmitters accepts 16-bit-wide or 10-bit-wide parallel data from the chip core and then serializes this parallel data into a serial steam that is sent off chip through a high-quality differential output port.

Similarly, each of the four receivers accepts serial data through a sensitive differential input port and de-serializes the serial stream into either 16-bit-wide or 10-bit-wide parallel data that is sent to the chip core.

The transmitter implements a 3-tap equalizer and the receiver incorporates a programmable equalizer to compensate for channel impairments.

Key Features

• NLIP™ SerDes technology is silicon-proven across several process generations,
  including TSMC 40nm G.
• NLIP™ SerDes technology is product-proven across several mass-production products.
• Power-efficient design dissipates very low power
• Wide data-rate range and support of single- or multiple-lane configurations
  addresses multiple applications
• Adjustable transmit equalization compensates for channel impairments
• Adjustable receiver equalization complements transmit equalization
• PRBS generator and checker improve testability
• Programmable I/O polarity and lane ordering ease board layout
  

Supported Standards

• 10G KR
• 10G XFI
• RXAUI
• XAUI
• QSGMII
• SGMII
• 8.5G Fibre Channel
• For other standards, please contact NetLogic Microsystems

Technology

• TSMC 40nm G CMOS process
• TSMC 28nm development is underway
• Supports FCBGA packaging
• Design by 0.9V/1.8V for core and IO device

Test Features

• On-die PRBS generator and checker
• Supports AC-JTAG testing
• Provides diagnostics capability through digital circuitry
• Supports several loopback modes to test transmitter and receiver

Deliverables

• Datasheet
• Integration guidelines
• Verilog model
• LEF abstract
• GDSII layout and mapping files
• LVS SPICE netlist
• STA timing model
• IO SPICE model

Implementation Details

The SerDes macro is implemented in the 40nm TSMC generic process. The macro operates off of 0.9V and 1.8V supplies. It employs a programmable, low-jitter PLL and a user-selectable 10/16-bit parallel interface to provide maximum design flexibility.