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10G PHY/SerDes for X2 / XENPAK Optical Modules Applications
This family of CMOS devices for 10-Gbps serial to 4-lane XAUI SerDes is designed for use inside optical modules including the XENPAKs, XPAKs and X2 form factors.
Benefits
- Best-in-class power consumption
- Optimized for XAUI-based optical modules (XENPAK, X2 and XPAK)
- Best-in-class package size
- Meets all XAUI and 10G jitter specs, XENPAK specs
- Robust MDIO interface allowing integration in to system operating systems
- Uses well established packaging and processing technology resulting in
high quality and reliability
- Fully qualified and shipping to end-customers
- Low power latency of 120ns
| Puma AEL1001 |
10G/XAUI LAN PHY/SerDes |
- 10GbE and 10G Fibre Channel LAN PHY/SerDes
(10G/XAUI) for XENPAK, X2 and XPAK optical modules
- 13x13mm Package
- 800 mW power consumption
- Integrated limiting amplifier
- Multiple loop-back modes
- Full support for XENPAK, IEEE, and customer-specific register requirements
- Pin compatible with AEL1004/AEL1010
- Built-in PRBS and BER Features
- MDIO, JTAG and SDA/SCL physical interfaces
- Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector
- Programmable bit and lane ordering
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| Puma AEL1004 |
10G/XAUI LAN/WAN PHY/SerDes |
- 10GbE and 10G Fibre Channel WAN PHY/SerDes
(10G/XAUI) for XENPAK, X2 and XPAK optical modules
- 13x13mm Package
- Low power dissipation enables higher-power long range optics for 10GBASE-LW/- EW/-ZW and DWDM modules
- Pin-compatible with AEL1001/AEL1010
- Meets IEEE XAUI Jitter Tolerance specifications for use in XENPAK, X2 and XPAK optical modules
- Integrated limiting amplifier improves receive sensitivity
- Reference Clock clean-up circuit allows loop timing capability in WAN mode
- Programmable bit polarity allows flexible board layout
- Fewer power supply filtering components eases board layout and reduces cost
- Adjustable XAUI TX pre-emphasis and integrated 10G RX equalization enables flexible board layout
- Interoperability verified with XFP modules from all leading optical modules manufacturers
- On-board packet generator and checker enhances testability and trouble-shooting capabilities
- MDIO, JTAG and SDA/SCL physical interfaces
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| Puma AEL1010 |
10G/XAUI LAN/WAN PHY/SerDes with integrated VCSEL driver |
- 10GbE and 10G Fibre Channel PHY/SerDes (10G/XAUI) for XAUI-based optical modules (X2, XENPAK, XPAK)
- 13x13mm Package
- Enhanced 10G receiver with integrated limiting amplifier and equalization circuit
- Integrated WAN Interface Sub-layer (WIS) IEEE 802.3ae Clause 50-compliant
- Pin compatible with AEL1001, AEL1004
- Integrated clock synthesizer allows 156.25MHz to be synthesized from a 50 MHz input or a 155.52MHz source
- Multiple loop-back modes
- Full support for XENPAK, IEEE, and customer-specific register requirements
- MDIO, JTAG and SDA/SCL physical interfaces
- Built-in PRBS and BER Features
- Support for jumbo frames
- Programmable bit and lane ordering
- SONET-quality jitter performance
- Integrated laser driver for 850nm VCSELs
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| Puma AEL2005 |
10G/XAUI LAN PHY/ SerDes with EDC (10GBASE-LRM) |
- 10GbE PHY/SerDes (10G/XAUI) for XENPAK and X2 modules
- 15x15mm Package
- Integrated EDC fully compliant with 802.3aq specifications
- Pre-emphasis and programmable rise/fall times on 10G TX side
- Programmable rise/fall times
- Integrated clock synthesizers allows 156.25MHz to be synthesized from a 50 MHz source
- Built-in PRBS and BER Features
- Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector
- TX pre-emphasis on XAUI interface
- Programmable bit and lane ordering
- SONET-quality jitter performance
- Multiple loop-back modes
- MDIO, JTAG and SDA/SCL physical interfaces
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May require a
non-disclosure
agreement. |
