|
10G PHY/SerDes for XFP Applications
This family of CMOS devices for 10-Gbps serial to 4-lane XAUI SerDes is designed for use with XFP modules on line-cards and Network Interface cards (NICs) in LAN, WAN, MAN and SAN applications (including 10G FC).
Benefits
- 800 mW/channel power consumption
- Optimized for line card/NIC applications with XFP optical modules
- Best-in-class package size
- Highly integrated functionality resulting in smaller “effective footprint”
- Robust 10G XFI design allows up to 15" of FR4 trace plus 1 connector to XFP module
- 10G Fibre Channel compatible
- Fully qualified and shipping to end-customers
- Low latency of 120ns
| Puma AEL1002 |
Single Channel XFI/ XAUI LAN PHY/SerDes |
- 10GbE and 10G Fibre Channel PHY/SerDes (10G/XAUI) for line-cards and NICs with XFP modules
- 13x13mm Package
- 800 mW power consumption
- Low power dissipation enables denser line cards with more 10G optical ports
- Adaptive receive equalization on 10G RX port
- Integrated limiting amplifier
- Programmable rise/fall times on 10G TX side
- Pin compatible with AEL1005, AEL1010
- Built-in PRBS and BER Features
- Support for 15" of FR4 plus 1 connector (XFP to PHY)
- Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector
- Programmable bit and lane ordering
- Proven interoperability with XFP modules from several vendors
|
| Puma AEL1005 |
Single Channel XFI/XAUI LAN/WAN PHY/SerDes |
- 10GbE and 10G Fibre Channel PHY/SerDes (10G/XAUI) for line-cards and NICs with XFP optical modules
- 13x13mm Package
- Low power dissipation enables denser line cards with more 10G optical ports
- Pin compatible with AEL1002, AEL1010
- Integrated WAN Interface Sub-layer (WIS) IEEE 802.3ae Clause 50-compliant
- Programmable bit polarity allows flexible board layout
- Fewer power supply filtering components eases board layout and reduces cost
- Adjustable XAUI TX pre-emphasis and integrated 10G RX equalization enables flexible board layout
- Interoperability verified with XFP modules from all leading optical modules manufacturers
- On-board packet generator and checker enhances testability and trouble-shooting capabilities
- MDIO, JTAG and SDA/SCL physical interfaces
|
| Puma AEL1010 |
Single Channel XFI/ XAUI LAN/WAN PHY/ SerDes |
- 10GbE and 10G Fibre Channel PHY/SerDes (10G/XAUI) for line-cards and NICs with XFP optical modules
- 13x13mm Package
- Low power dissipation enables denser line cards with more 10G optical ports
- Enhanced 10G receiver with integrated limiting amplifier and equalization circuit
- Integrated WAN Interface Sub-layer (WIS) IEEE 802.3ae Clause 50-compliant
- Pin compatible with AEL1002, AEL1005
- Integrated clock synthesizer allows 156.25MHz to be synthesized from a 50 MHz input or a 155.52MHz source
- Multiple loop-back modes
- Full support for XENPAK, IEEE, and customer-specific register requirements
- MDIO, JTAG and SDA/SCL physical interfaces
- Built-in PRBS and BER Features
- Support for jumbo frames
- Programmable bit and lane ordering
- SONET-quality jitter performance
|
| Puma AEL1020 |
Dual Channel XFI/XAUI LAN PHY/SerDes |
- 10GbE PHY/SerDes (10G/XAUI) for line-cards and NICs with XFP modules
- 16x16mm Package
- Low power dissipation enables denser line cards with more 10G optical ports
- Enhanced 10G receiver with integrated limiting amplifier and equalization circuit
- TX pre-emphasis on the 10G and XAUI sides
- Integrated clock synthesizer allows 156.25MHz to be
synthesized from a 50 MHz input
- Multiple loop-back modes
- Full support for XENPAK, IEEE, and customer-specific register requirements
- MDIO, JTAG and SDA/SCL physical interfaces
- Built-in PRBS and BER Features
- SONET-quality jitter performance
- Programmable bit and lane ordering
|
|
May require a
non-disclosure
agreement. |
