NetLogic Microsystems’ Multi-Core Processor Solutions
NetLogic Microsystems offers highly scalable processor solutions that allow system designers the flexibility to optimize performance, power consumption and cost for a wide variety of applications. The company offers a range of high performance, highly integrated, feature-rich processor solutions.
These processor-based solutions provide high throughput, power efficiency, application and content awareness and security for the evolving global connectivity network. Our products serve the infrastructure, enterprise and consumer multimedia markets with a wide range of price and performance configurations.
The company offers a full line of products including:
XLP Processor™ Family – The XLP Processor™ is a third-generation architectural enhancement to the industry-leading Multi-Core, Multi-Threaded XLR Processor® family. The XLP is fabricated using 40-nm technology and offers processor core frequencies from 500 MHz to greater than 2GHz, providing a 3x performance per watt improvement over its XLR predecessor. The XLP is software backward-compatible with the XLR and XLS® Processor families. The XLP Processor is a highly-scalable device that incorporates key functions of a high-end communication system, including wired and wireless security, networking, storage, data center acceleration, load balancing, and other acceleration engines.
XLR Processor® Family – NetLogic Microsystems' Multi-Core, Multi-Threaded XLR Processor® family is a very
high throughput, feature-rich processor solution for a wide variety of infrastructure equipment
and enterprise systems. Our XLR Processors enable applications such as integrated security,
Web services, virtualized storage, load balancing and server offload, as well as content and
application aware, multi-service routing and switching.
XLS® Processor Family – NetLogic Microsystems' Multi-Core, Multi-Threaded XLS Processor® family offers
mid- to entry-level derivative versions of the XLR architecture. The XLS Processor leverages
the XLR’s performance, scalability and technology innovations and incorporates additional
advanced connectivity standards. Our XLS Processors address applications that demand
smaller form factor and lower power consumption. Our XLS Processors are pin-compatible
within each series and software compatible across all XLS and XLR Processor families.
Silicon
NetLogic Microsystems’ advanced processors can deliver functionality, performance and cost that differentiate us from competitors across a broad range of markets and applications. We believe we accomplish this by tight integration of key technologies and an innovative architecture, including our power-optimized processor core, our thread processing technology, our on-chip Fast Messaging Network™, and the integration of various acceleration and security engines including: Autonomous Networking Acceleration Engine®, security encryption engines, compression/decompression engines and the media acceleration engine. The following elements are the key technologies and architectural features of our processor solutions.
Very Low Power Processor Core
Our processor cores are based on the standard MIPS® processor instruction set. However, we take advantage of our core microprocessor design heritage and expertise and significantly optimize our processor core architecture and implementation. We utilize very low power microprocessor design techniques and utilize low voltage and low leakage cell libraries, which allow us to incorporate high power efficient cores. Given the importance of power efficiency, our Ultra Low-Power Processors family of processors implements some of our most advanced low power design techniques.
Thread Processor Technology
Our thread processing technology allows us to integrate four tightly integrated hardware threads, each thread acting as a virtual central processing unit (vCPU™), in a single processor core. Unlike single-threaded designs, our architecture is well suited for network-oriented processing environment and is capable of significantly reducing the delays associated with memory latency and increases performance. Multi-threading technology enables other threads to continue to efficiently process instructions when one thread becomes stalled while waiting for memory data to return. As a result of implementing thread processor technology, our processors are capable of much higher throughput as well as better execution of software coding versus traditional single thread processing technology by the use of simultaneous operations in multi-thread technology.
Fast Messaging Network™ Technology
Our Fast Messaging Network™ is a fundamentally different way of enabling on-chip communications, allowing our Multi-Core, Multi-Threaded architecture to deliver extremely efficient parallel data processing performance. This on-chip communications architecture is highly scalable and designed to eliminate communications bottlenecks between processor cores, acceleration engines, interfaces and memory. The Fast Messaging Network operates at core frequency up to 1.4GHz and supports up to 1.75 Billion messages per second.
Autonomous Networking Accelerators® and Security and Compression Engines
As more and more processing requirements are placed on-chip, efficient processor resource sharing becomes a significant performance challenge. This results in ineffective workload distribution and management. Many of today’s multiprocessors utilize a standard direct memory access (“DMA”) ring in which all CPU resources will attempt to access a single data structure. This is extremely inefficient since it frequently requires the use of data locks, thus consuming an unusually large percentage of CPU time simply to access the data without completing any meaningful work. It is also not uncommon for a subset of processor resources, which could have been used for more productive output, to be dedicated simply to manage the workload distribution burden. In either case, throughput potential is wasted. To address this issue, our processors are equipped with highly optimized acceleration engines that offload the processor cores and streamline processing efficiency.
Our Networking Accelerator supports higher-layer programmable parsing, packet direction management, checksum verification and load balanced packet distribution across the multiple processor threads. Our proprietary Autonomous Security Acceleration Engine® completely off-loads encryption/decryption and authentication-related hashing operations from the central processing cores, enabling up to 11.6 Gbps of bulk cryptographic processing and supports industry-standard security protocols such as IPsec and security sockets layer (“SSL”).
Our autonomous on-chip Advanced Encryption Standard (AES) Cryptography Engine, for both our Ultra Low-Power Processors media and multi-core processors, supports 128-bit AES in ECB, CBC, CFB and OFB modes, and uses the data transfer capabilities of a DBDMA Controller to augment the encryption/decryption functions. Decryption functionality implemented in on-chip hardware enables device manufacturers to avoid slowing down the processor with the security function and frees up processing power for other device requirements. For control plane applications, our security engine supports virtual private network (VPN) solutions for both IPsec and SSL, allowing designers the flexibility in selecting security configurations and performance options.
Our Autonomous Compression/Decompression Engine offloads the compression functions to an autonomous IP block, freeing up additional processing capacity within each core for greater efficiency and throughput.
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