Puma AEL1002
10GbE/10GFC LAN PHY/SerDes

NetLogic Microsystems' Puma AEL1002 device is a single channel CMOS physical layer (PHY) transceiver optimized for use in XFP-based 10Gbps line-card applications. Its XFI- compliant serial interface supports interfacing with XFP modules at 10 Gigabit Fibre Channel data rates and its flexible system side interconnect supports interfacing with MACs and ASICs using a XAUI interface.

The AEL1002 device uses NetLogic Microsystems' high-density PHY technology to offer an attractive combination of high performance (10 Gbps) and low power consumption (800 mW). Full PCS, PMA, and XGXS sub-layer functionality is provided through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock drivers, multiple loop-back features and PRBS generation & verification for both the line side and the system side.

This combination of low power and attractive features enables flexible board design and accelerates the deployment of dense 10G line cards for both 10 Gbps Ethernet and Fibre Channel applications.

Benefits

• Low power dissipation enables denser line cards with more 10G optical ports
• AEL1005 pin-compatible
• Programmable bit polarity allows flexible board layout
• Fewer power supply filtering components eases board layout & reduces cost
• Ideal for dual-standard (10GbE & FC) applications
• Adjustable XAUI TX pre-emphasis and integrated 10G RX equalization
  enables flexible board layout
• Interoperability verified with XFP modules from all leading optical modules manufacturers
• On-board packet generator & checker enhances testability and trouble-shooting capabilities

Features

• 800 mW power consumption
• Programmable swing on XAUI and 10G TX
• Integrated adaptive equalizer for XFI signal recovery after 15”FR-4 with one connector
• On-chip clock generation and data recovery
• Dual reference clock frequency support
  (10GbE, 10G FC)
• Jumbo frames supported
• Programmable bit & lane ordering
• Adjustable XAUI transmit pre-emphasis for 40” FR4
• Multiple loop-back modes
• Packet, PRBS, CJPAT and CRPAT
  generators and checkers
• MDIO, JTAG & SDA/SCL physical interfaces
• 144 pin, 13x13mm PBGA package
• Low latency of 120ns

Applications

• 10 Gigabit Ethernet LAN/MAN/SAN Systems
• 10 Gigabit Fibre Channel SAN Applications
• 10GbE Add/drop Multiplexers
• 10GbE Switch/router Backbones
• 10GbE Hubs and Repeaters
• 10GbE/10Gb FC Test Equipment
• 10GbE Terabit Routers
• 10GbE NICs
• 10Gb FC HBAs

COPYRIGHT 2007-2009. NETLOGIC MICROSYSTEMS, INC.   ALL RIGHTS RESERVED