Puma AEL1005
10GbE/10GFC LAN/WAN PHY/SerDes

NetLogic Microsystems' Puma AEL1005 device is a WAN Interface Sublayer (WIS)-enhanced single channel CMOS physical layer (PHY) transceiver optimized for use in XFP-based 10Gbps line-card applications. Its XFI-compliant serial interconnect, which supports interfacing with XFP modules either in LAN/SAN environments or using an integrated IEEE 802.3ae WIS compliant implementation, enables transmission of 10 Gigabit Ethernet traffic directly across SONET-based optical networks.

The AEL1005 device uses NetLogic Microsystems’ high-density PHY technology to offer an attractive combination of high performance (10Gbps) and low power consumption (in LAN mode). Full PCS, PMA, and XGXS sub-layer functionality is provided through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock drivers, multiple loop-back features and PRBS generation & verification for both the line side and the system side.

To enable the optional WIS support, the AEL1005 device includes clocking modifications allowing support for the 10 Gigabit Ethernet data rates of 10.3125 Gbps and the SONET data rate of 9.953 Gbps in an implementation requiring only a single external clock input, which could be either an XO or a VCXO. In both cases, SONET-grade jitter transfer compliance is achieved, while the integrated WIS digital block meets the requirements of clause 50 of the IEEE 802.3ae standard.

Benefits

• Low power dissipation enables denser line cards with more 10G optical ports
• AEL1002 pin-compatible
• Programmable bit polarity allows flexible board layout
• Fewer power supply filtering components eases board layout and reduces cost
• Adjustable XAUI TX pre-emphasis and integrated 10G RX equalization
  enables flexible board layout
• Interoperability verified with XFP modules from all leading optical modules manufacturers
• On-board packet generator & checker enhances testability and trouble-shooting capabilities
  
  

Features

• Best-in-class power consumption
• Programmable swing on XAUI and 10G TX
• Integrated adaptive equalizer for XFI signal recovery after 15” FR-4 with 1 connector
• Integrated clock synthesizer for operating with a single clock source
• Jumbo frames supported
• Loop timing capability for WAN mode
• Programmable bit and lane ordering
• Adjustable XAUI transmit pre-emphasis for 40” FR4
• Multiple loop-back modes
• Packet, PRBS, CJPAT & CRPAT generators & checkers
• MDIO, JTAG & SDA/SCL physical interfaces
• 144 pin, 13x13mm, 1mm pitch PBGA package
• Low latency of 120ns

Applications

• 10 Gigabit Ethernet LAN/MAN/SAN Systems
• 10 Gigabit Fibre Channel SAN Applications
• 10GbE Add/drop Multiplexers
• 10GbE Switch/Router Backbones
• 10GbE Hubs and Repeaters
• 10GbE/10Gb FC Test Equipment
• 10GbE Terabit Routers
• 10GbE NICs
• 10Gb FC HBAs

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