Puma AEL2005
10GbE LAN PHY/SerDes with EDC

NetLogic Microsystems' Puma AEL2005 device is a physical layer transceiver with an integrated Electronic Dispersion Compensation (EDC) engine - compliant with IEEE802.3aq specifications. The device integrates NetLogic Microsystems’ industry-leading SerDes/PHY technology from the earlier generation of 10G PHY/SerDes devices (AEL1001 – 1006) with an innovative low-power EDC engine with up to 5db of margin over the symmetric stress test pulse sensitivity specifications defined in the 10GASE-LRM standard.

The NetLogic Microsystems Puma AEL2005 device provides full PCS, PMA, and XGXS sub-layer functionality through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock drivers, multiple loop-back features and PRBS & Ethernet frame generation & verification for both the line side and the system side.

Benefits

• The 10x10mm QFN is the industry’s smallest integrated EDC/PHY/SerDes – making it ideal for use in dense applications
• High performance EDC engine provides up to 6dB of margin with IEEE 802.3aq defined stress test pulses
• Proven interoperability with SFP+ SR modules from several vendors
• Proven interoperability with SFP+ LRM modules
• Proven interoperability with several linear ROSAs
• EDC and pre-emphasis functions allow for up to 15m of twin-ax copper cable transmission
• Low latency and low power dissipation makes it ideal for use in datacenter Ethernet applications
• Low power dissipation allows use inside X2 optical modules
• Meets IEEE XAUI Jitter Tolerance specifications for use in XENPAK & X2
• Enhanced BIST features simplify optical modules testing

Features

• Best-in-class power consumption
• On-chip clock generation and data recovery
• Capable of operating with 50 MHz reference clock
• TX pre-emphasis and RX equalization on the XAUI interface
• 1GbE capability
• Adjustable XAUI transmit pre-emphasis
• Meets 10GBASE-LRM requirements
• Multiple loop-back modes
• Packet, PRBS, CJPAT and CRPAT generators and checkers
• MDIO, JTAG & SDA/SCL physical interfaces
• 124 pin, 10x10mm, QFN package
• 196 pin, 15x15, BGA package (1mm ball pitch)
• EDC engine proven interoperability with several
• SFP+ modules and several linear ROSAs
• RoHS 5/6 and RoHS 6/6
• Low latency of 120ns

Applications

• X2 Modules for Switches and Routers with the 10GBASE-LRM Applications
• XENPAK Modules for Switches and Routers with 10GBASE-LRM Applications
• With SFP+ Modules for 10GBASE-LRM Applications
• With SFP+ Modules for 10GBASE-SR and – LR Applications
• With direct-attached copper SFP+ Applications
• Datacenter Ethernet Applications

COPYRIGHT 2007-2009. NETLOGIC MICROSYSTEMS, INC.   ALL RIGHTS RESERVED